1. Field of the Invention
The present invention relates to a fabrication method for an integrated circuit device. More particularly, the present invention relates to a fabrication method for a flash memory cell.
2. Description of the Related Art
FIG. 1 is a schematic, cross-sectional view of a flash memory cell according to the prior art. Beside an oxide layer not being shown in the Figure, the conventional flash memory cell, as illustrated in FIG. 1, comprises a polysilicon gate 104, a silicon nitride layer 102, a source region 106a and a drain region 106b, wherein the source/drain region 106a, 106b are formed near the two sides of the silicon nitride layer 102 in the substrate 100.
There are two approaches for the above flash memory cell to perform the programming operation. One approach is to apply a positive voltage to the polysilicon gate 104 and a lesser positive voltage to the drain region 106b. Hot electrons are thus injected into and trapped in one end of the silicon nitride layer 102 near the drain region 106b. Another approach is to apply a positive voltage to the polysilicon gate 104 and a lesser positive voltage to the source region 106a. The hot electrons are injected onto and trapped in one end of the silicon nitride layer 102 near the source region 106a.
One drawback of the conventional flash memory cell is that the hot electrons do not necessarily stay in the two ends of the silicon nitride layer 102. These hot electrons sometimes redistribute themselves in the silicon nitride layer 102. The occurrence of redistribution not only poses difficulties in the reading operation, it also leads to the serious problem of an over-erase.